OT3135 Low Power PLL for TSMC 40nm ULP

The OT3135 is a flexible, low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for TSMC 40nm, ULP CMOS processes.

ot3135 180nm ULP PLL
ot3135 40nm ULP PLL

Features

  • Wide range M, P, and N integer dividers.
  • 40MHz – 600MHz output frequency range.
  • Input frequency range 1.4MHz – 32MHz.
  • 18pS RMS cycle to cycle jitter.
  • Lock-detect function.
  • Optional bypass function.
  • Level shifted IO.
  • Well-defined, fast startup behavior.
  • -40°C to 125°C temperature operation.
  • Small area: 0.03mm2 in 40nm CMOS.
  • 100µW typical power dissipation.
  • 0.82-1.1V digital and analog supplies.
  • Silicon proven.

Contact info@ot1.com for further information.