This project required a custom 4 level logic library to be designed and integrated into a test chip and sent to MOSIS within 40 days.
The test design comprises several 8 bit 4 level logic ALU’s, plus an equivalent function implemented in binary standard cell logic for comparison.
This device used full custom layout for the four level logic (as shown right).
The equivalent binary ALU’s were implemented using standard cells and standard cell place and route.
