ROBERT JOHN HEATON
 
Dana Point, California

  (see also visual resume)

OBSIDIAN TECHNOLOGY, Laguna, CA (5/96 - Present) Founder

As a hands on founder of this small consulting firm involved in all aspects of engineering, sales and marketing. For further information see www.ot1.com.

• Developed 10Gb Ethernet architecture and simulation for 10G startup and participated in series A fund raising.

• Developed MorphoTech reconfigurable SIMD computer architecture under DARPA contract. Activities included DARPA proposal, the 8x8 core CPU and dynamic routing architecture, architecture support tools such as text based assembler in Perl and graphic assembler/simulation engine in TCL/TK. Developed full custom CMOS multiplier for the CPU multiply function.

• Developed a 1.8 volt, 8 bit, 125MHz pipelined Analog to Digital Converter in 0.18µ CMOS.

• Developed 1000BaseT DSP/Analog Front End Engine IP in Matlab/Simulink and C++. Sold to AMD, LSI Logic, Cadence Design, TDK etc.

• Developed CHDL proprietary high speed Mixed Signal Simulator in C++.     

• Provided a key consulting position for a major telecommunications company moving into the LAN device business.

• Developed IIRGen, an optimizing digital filter assembly code compiler for Texas Instruments processors.

STANDARD MICROSYSTEMS CORP, Irvine, CA (11/90 - 4/96)
Senior Director of Engineering

Responsible for Engineering development within SMC's $250M LAN adapter business including LSI design, board design, CAD, board test and LSI test development. Leadership of an organization of sixty Engineering and support staff. Introduced major improvements to group performance in terms of productivity, quality and technology.

• Changed the company's silicon sourcing strategy from reliance on AT&T processing to generic foundries substantially reducing costs and providing viable alternative sourcing.

• Closed several joint development agreements with a total value in excess of $20M.

• Integrated design and LSI test development flow reducing test development time for mixed signal chips from over a year to under three months.

• Established close relationship with University of California at Irvine (UCI). This led to SMC hiring up to 15 Engineering interns concurrently and 8 "Star" graduates which now form the backbone of the Hardware Engineering capability. Also established an SMC fellowship program. Chairman of Engineering Corporate Affiliates.

• Managed the transition of the Engineering group during the sale of the Western Digital LAN business to Standard Microsystems. Added a number of key functions to the group at this time including an analog LSI capability, custom LSI layout, and PCB layout. Moved from reliance on design consultants to focus on in-house design.

• Increased the visibility of the Company at IEEE 802.3, 802.5, and ATM public forums. Invented and presented the 4T+ Fast Ethernet category 3 signaling scheme to 802.3 which has been adopted by the IEEE and patented by the Company.

• Put in place detailed formal design procedures and a formal quality enhancement program.

• Continued to make significant technical and product definition contributions. This included the five successful LSI device definitions, Token Ring equalizer design methodology, Elite Ultra Simultasking transmit underrun hardware, adoption of PCI bus as internal adapter bus, Ethernet PCMCIA power reduction scheme, daisy chained Ethernet card. Worked with interns on SRAM, DRAM, and ROM designs. Developed World’s first CardBus adapter.

EUROPEAN SILICON SYSTEMS, London, UK and San Jose, CA. (3/86 - 10/90)
Director of Research and Development / Design Manager

• Gained extensive customer interface experience in developing the business from start up through the first 150 designs in the Northern European and North American design centers.

• Responsible for set up and day-to-day management of the Northern European design center. Made significant contributions to the company's design flow methodology defining the Solo monitor software and the automated chip data base processing scheme.  Designed the company's first chip product. Supervision of nine staff

• Specified and supervised the development of a number of software tools including L2I, a portable HDL compiler and logic simulator, and BDT, the company's unique low-cost bulk chip layout transmission network. Personally wrote the BDT geometric layout data compressor which was patented by the company. Completed around 20 small C and Pascal programs for data conversion etc.

ACORN COMPUTERS, Cambridge UK. (6/83 - 2/86)
Manager VLSI Design

• Established VLSI design group and was responsible for the design of the ARM chip set now in use by Intel, TSMC, NEC, Philips, Texas Instruments and over 100 other corporations. The ARM is now used in most cell phones. My responsibilities included hiring the staff, buying the equipment and CAD software, writing additional software, managing silicon vendors, and day to day management.

• Architected the ARM data path and data flow. Personally designed most of the ARM CPU at a transistor level including the ALU, register file, PSR, the PLA's (in Pascal), the IO cells, and the Acorn standard height cell library. Responsible for implementation of support chips including the memory controller, interrupt controller, and video controller. All four large, full custom, hand crafted circuits were fully functional at first silicon. 

• It was my initiative to sell the design rights to VLSI Technology (Philips) and I was responsible for the contract negotiations.

PHILIPS, Zurich Switzerland. (6/82 - 6/83)
Project Leader  

 Led the design of the PCF8577 multimode I2C bus LCD display driver chip from specification to tape out. This involved very low power 3V mixed analog/digital full custom CMOS design.

TEXAS INSTRUMENTS, Houston TX and Bedford England. (6/79 - 6/82)
Design Engineer

Designed the TAL002/TAL004 gate array masters and set up design flow. These were TI's first successful gate array devices and were the first gate array devices in Europe to be supported with LVS layout checking in the design flow. I was responsible for TI's STL gate array soft macro library. Wrote a logic minimizer tool in Pascal.

GARDNERS TRANSFORMERS, Christchurch UK. (5/72 - 10/75)
Development Engineer

Joined the design team at 17 years of age after a one year apprenticeship. Designed about 20 custom switch mode power supplies including direct off line supplies. Also designed a number of transformers and inductors.

EDUCATION:  

UNIVERSITY OF SURREY, Guildford UK. 1979: B.Sc. Electronics. Grade: 2(1).

C.E.R.N, Geneva Switzerland. (8/77 - 8/78) Student Engineer (3rd year of a 4 year University course)

Designed a number of control systems for MW level DC power supplies. Developed and wrote a paper on a new form of very high accuracy DC-Current transformer. This is now used by C.E.R.N on many power supplies in the Large Electron-Positron accelerator ring.

STANFORD/AEA: Mini MBA course.

References furnished on request