USB Power Delivery BoardUSB Power Delivery Development/Test Board

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 The OTS9102 USB Power Delivery Demonstration and Development board version 4.4 is designed to assist in the development and testing of early market Power Delivery products.

The basic demo configuration of the board can be used learning system operation, compatibility testing, and production functional testing.

Source code is available for both the FPGA, and the CMOS Analog Front End chip as separate products.

Basic Features

  • 3A current available at 5V, 12V, and 15-20V.
  • Headers for investigation of critical PD signals.
  • Jumper configurable for provider or consumer roles at boot time.
  • Power terminals for consumer load.
  • 3.5" x 7" board has a connector for host interface.
  • Parallel USB standard PD A and micro AB connectors provided for PD.
  • A micro AB connector is provided for simulating PC or peripheral USB communications.
  • An Opal Kelly FPGA daughter board provides a well established FPGA development and USB host interface environment.
  • Supports 1.2 PD standard (including swap)
  • Uses Obsidian's OTC9102 analog front end chip.








  • USB PD Demonstrator. Key signals from the OTC9102 chip are available on headers. Hence the board provides a demonstration platform for the chip, and associated RTL. Available host software can drive the chip in step by step mode to allow protocol operation to be followed. 
  • USB PD Product Testing. Board can be configured as provider or consumer for bench testing other PD products. Since Obsidian has tested this board at the USB IF IOP meetings the board may be used to support compatibility testing.
  • Development Board. FPGA capability is provided by a daughter board with USB host interface API. This also works with the Xilinx development environment as platform for maintenance of the protocol logic and policy code.
  • Protocol Sniffer for debugging USB Power Delivery systems. With an available application, when daisy-chained between two USB PD systems, the Sniffer board produces an easy to read mnemonic listing of captured packets on a PC.
  • Traffic Generator. The system can be configured to generate arbitrary packet sequences, with custom timing, using a simple packet assembly API in C++. The primary use for this is in system debug and protocol error testing.


Price: $3300 per unit + shipping

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