OT3130 800MHz PLL for TSMC 152nm

The OT3128 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the TSMC  0.152µ digital or high voltage CMOS processes. The design features an advanced multi-stage balanced VCO for exceptional cycle to cycle jitter performance, and 20µS start time.

Pricing is $17K for multi-use!




  • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
  • 40MHz – 800MHz output frequency range.
  • Compare frequency range 8MHz – 32MHz.
  • Optional pre-scaler.
  • 15pS RMS cycle to cycle jitter at 800MHz.
  • Lock-detect function.
  • Bypass function.
  • 20µS well defined fast startup behavior.
  • -40°C to 140°C temperature operation.
  • Available divider selection program.
  • Small cell area: 0.04mm2 in 0.152µ CMOS.
  • 4mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.152µ CMOS process compatibility.
  • Only 1.8V transistors are used in the design.
  • Silicon proven architecture.

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ot3130 PLL Layout