LVDS Transmit and Receiver Cells
OT3910bjc is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to point communication on the Austriamicrosystems AMSC18 digital process. Compatible power pads are also provided.
The transmit driver cell translates 1.8V core logic signal levels to LVDS levels with a typical differential output swing of 350 mV. The receiver cell translates LVDS levels, with a typical differential input threshold of of above 100mV, to 1.8V core logic signal levels. A reference cell is also provided to produce appropriate bias currents voltage reference signals for the transmit and receive cells.
- Meets or exceeds the TIA/EIA-644 LVDS standard.
- Driver, Receiver, Bias, and Power cells included.
- Greater than 400Mbs data rate.
- 1.8V core voltage, 3.3V IO voltage.
- Receive fault detection.
- 0.2ns differential pulse skew.
- 0.8ns receive propagation delay.
- Metal layout outline.
- Flat gds layout (for some IP this is delivered to the fab for integration).
- Verilog model.
- Spice flat netlist.
- Basic spice testbench. Allows for verification of basic function.
- Integration notes, and integration consulting support.
- Test implementation notes.
- Available support for manufacturing and characterization.
- Available translation to your design style.
- Available on-site design review.
- Source licensing available.
Simple License Options:
IP Multi-Use Package
- Allows usage on multiple designs.
- Flat gds layout, netlist, integration notes, data sheet, layer map.
- Available on site consulting and design integration training / support.
- No Royalties.
- Full source ownership and required documentation and training to allow modification, derivation, porting.
- Hierarchical gds layout, schematic, netlist, integration notes, data sheet, design notes, test benches, layer map.
- Available on site consulting and design integration training / support / porting to your system.
- No Royalties.