OT0102af Trimmed Low Power Bandgapbgs

The BG102 is a 1.2V CMOS low power, high precision CMOS band gap cell designed for use in a wide variety of mixed signal device applications.

The base design is implemented with lambda-based sizing and portable layout constructs for maximum ease of process porting. The architecture supports operation down to 1.5V.

Features

  • Precision of ±0.2% over process, temperature, and voltage.
  • 4 Bit temperature coefficient trimming.
  • Optional 4 bit voltage trimmer.
  • 1.2V output.
  • DC PSRR -100dB, Peak PSRR –20dB.
  • 15µV RMS output noise
  • 3.3 or 5 Volt supply voltage options with option for separate substrate connections.
  • Power down input.
  • Uses manufacturer supported bipolar structures.
  • 500nA positive temperature coefficient current source.
  • Bullet-proof start-up circuit.
  • Stable to infinite capacitive load.
  • Start-up time less than 5µS.
  • Base cell area 0.03mm2 in 0.35µ CMOS.
  • 1P3M CMOS process compatibility.

 

Typical Applicationsbgpx200

  • Temperature reference.
  • LDO.
  • Bias generation.

Service Features

  • 5 Weeks lead time for process ports.
  • Available support for manufacturing and characterization.

Standard Deliverables:

  • Metal layout outline.
  • Flat gds layout (for some IP this is delivered to the fab for integration).
  • Verilog model.
  • Spice flat netlist. 
  • Basic spice testbench. Allows for verification of basic function.
  • Integration notes, and integration consulting support.
  • Test implementation notes.

Service

  • Available support for manufacturing and characterization.
  • Available translation to your design style.
  • Available on-site design review.
  • Source licensing available.

Simple License Options:

IP Multi-Use Package

  • Allows usage on multiple designs.
  • Flat gds layout, netlist, integration notes, data sheet, layer map.
  • Available on site consulting and design integration training / support.
  • No Royalties.

Source Ownership

  • Full source ownership and required documentation and training to allow modification, derivation, porting.
  • Hierarchical gds layout, schematic, netlist, integration notes, data sheet, design notes, test benches, layer map.
  • Available on site consulting and design integration training / support / porting to your system.
  • No Royalties.