Products

OTC9115 USB 3.1 Cable Marker Chip

The OTC9115 is a complete, low cost, single chip cable marker for USB PD Type-C (baseband) cables. With low silicon area and just 4 IO’s the device is design exclusively for very high volume Type-C cables with basic marker requirements.

Features

  • USB PD 3.1 compliant.
  • Single chip solution - just two external capacitors.
  • 4 pin package.
  • PROM programmed through vendor message protocol.
  • Based on Obsidian’s mature PD technology.
  • Integrated PROM enables customized response to a wide range of vendor requirements.
  • Active Ra pull down only requires 10uA at 5V., but is <1K below 2V.
  • Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
  • Programming can be done after assembly into the cable. Fuse lock function.
  • Supports low cost 4 layer PCB assembly.
  • Supported with module level test program.
  • Package options: WLCSP-4, QFN-8, DFN-8, SOP23-5.
    IP licensing is available.

marker

Major Functions

  • Physical Layer. Based on Obsidian’s OTC9107 port chip physical layer, this provides CC line driving and reception without external components. It includes data slicer, activity detection, voltage level detection, and slew rate controlled driver.
  • LDO. Provides bandgap, and internal voltage regulation for the logic the physical layers. Power diodes also provide the required power isolation between two possible power sources (one at each end of the cable).
  • Oscillator. A low temperature drift 12MHz oscillator provides logic clocking when required. The provided test program automatically trims the oscillator during test for an overall frequency accuracy of ±5%.
  • Protocol Engine implements the low level protocol and logic phy functions required by the standard. Such as CRC generation and testing, 4b5b coding, BMC coding, clock recovery, and SERDES.
  • Marker State Machine. Provides the subset of device functions required to recognize vendor messages and return responses based on PROM data.
  • Programmed response. Will respond with Cert-Stat VDO and Cable-VDO with all relevant fields programmable.
  • Supporting Software in C form is available for rapid implementation of production test.

otc9115

USB PD Packet Generator API

Overview

Provided with the USB PD development system, this is a tool for sending custom packets. This is primarily used for setting up tests for the protocol. It enables custom generation of PD packets and packet spaces in a readable API. The primary goal is to automate much of the coding, decoding, CRC generation etc.

The code, written in C++, and compiled with Microsoft Visual Express "cl" command, connects to the system board through a USB interface. Typically a buffer of packet information is either sent repeatedly, or sent as a single shot.

The generator can be combined with the protocol analyzer (aka "sniffer") to debug PD protocol issues.

Example Code Fragments

Code Function
sendControlPacket(0,goodCRCAck); Queue a complete good CRC acknowledge packet with the id of 0.
preamble();
sop();
sendHeader(2,1,capabilities);
queueTxInt32(prof5V1p5A);
queueTxInt32(powerObject12V1A);
queueCrc();
eop();
Queue a more customized packet. In this case a capabilities packet with two data objects and the id code of 1. Note that the CRC is generated be the code.

for(int i=0;i<13;i++)
  qbits(32,0);

Combine C++ and API. In this example, queue 32 bits of "0" symbols, 13 times.

API Functions

initPacketBuild();

Typically the first statement in the API script, this function sets up the defaults for the API.

sendControlPacket(int id, int cntType);

Queue a full PD control packet with id and allowed control packet type. The control code is an integer as specified in the PD specification. Define statements are also included in the code to make these mnemonic.

preample();

Queue a full 64 bit PD preamble sequence starting with a "1".

sop();

Queue a PD start of packet sequence.

eop();

Queue a PD end of packet sequence.

sendHeader(int numObjects, int id, int headerType);

Queue a customized PD header sequence. numObjects is the number of 32 bit data object to be sent. id is the PD id of the packet. headerType is an integer specifying the data packet type and is compatible with the spec. These are also available as defines in the code.

bitRun(int numBits, int value);

Queue a PD run of uncoded bits.

queueTx(unsigned char);

Queue a PD data symbol. Data is a 4 bit number in the 4 lsb's representing 0-9 + special codes per the PD standard. The 4 bit code is converted into a 5 bit 4b5b symbol before queuing.

queueTxInt16(int);

Queue 4 PD data symbol, lsb first. Data is 4 bit numbers representing 0-9 + special codes per the PD standard. The 4 bit code is converted into a 5 bit 4b5b symbol before queuing.

queueTxInt32(int);

Queue 8 PD data symbols, lbs first. Data is 4 bit numbers representing 0-9 + special codes per the PD standard. The 4 bit code is converted into a 5 bit 4b5b symbol before queuing. 

timeGap(float time);

Queue a PD run of uncoded zeros for a specified time. Assumes 3.3uS per bit.

qBits(int numBits, int valueOfBits);

Queue a PD raw bit sequence up to 32 bits. Bit 0 of the value is sent first. No symbol coding is done.

queueCrc();

Queue a PD CRC. This function generates and queues a CRC from the applicable data in the packet. It must appear before the packet EOP.

portRole = (consumer|provider);

Set the rôle of the generated packets. This is a global int, not a function. Defines are provided for consumer and provider. This statement will normally be placed after the initial initPacketBuilt(); function. The default is provider.

dumpBin();

Dump the assembled packets to the screen in binary form. The high bit is dumped first such that the last bit output corresponds to the last bit sent.

writeC(char* fileName);

Dump the assembled packets to fileName in C unsigned char form.

Practical Example Code

initPacketBuild();
portRole=consumer;

sendControlPacket(0,goodCRCAck);

preamble();

sop();
sendHeader(2,1,capabilities);
queueTxInt32(prof5V1p5A);
queueTxInt32(powerObject12V1A);
queueCrc();
eop();


// delay
for(int i=0;i<15;i++) qbits(32,0);

sendControlPacket(2,goodCRCAck);
gapTime(10 uS);


sendControlPacket(3,accept);
gapTime(10 uS);

sendControlPacket(4,PS_RDY);

dumpBin();
writeC("tmp.txt");

 

API Defines

// Misc.
#define consumer 0
#define provider 1
#define specRev 0
#define portType 0

#define maxRetries 3

#define nS *1e-9
#define uS *1e-6
#define mS *1e-3

// Standard Based Control Symbols
// (actual bits sent)
#define SOP1         0x18
#define SOP2         0x11
#define SOP1SOP2     0x238
#define rSYNC        0x071
#define EOP          0x0d
#define RST1         0x07
#define RST2         0x19

// Control Message Codes
#define goodCRCAck 1
#define gotoMin 2
#define accept  3
#define reject  4
#define keepAlive 5
#define PS_RDY 6
#define getSourceCap 7
#define getSinkCap 8
#define protocolError 9
#define swap 10
#define cableODC 11
#define wait 12
#define resetCode 13

// Message Data Object Codes
#define fixed 0
#define programmable 1
#define variable 2
#define battery 3

// Header Data Packet Types
// Used when header length field is >0
#define capabilities   1
#define request        2
#define phyBist        3

// Coded Power Objects
#define numCapabilities 2
#define prof5V1p5A 0x0
#define powerObject12V1A   0x3c03c064

 

 

 

OTS9101: USB Power Delivery Transceiver, Sniffer, and Development Tool

The OTS9101 is a transceiver and logic development environment for power supply communication over a single conductor. The analog front end is based on Obsidian's OTC9102 IP demonstrator chip. The system is optionally supplied with application software for a variety of distinct tasks. Namely:

  • Protocol Sniffer for debugging USB Power Delivery systems. When daisy-chained between two USB PD systems, the Sniffer board produces an easy to read mnemonic listing of captured packets on a PC.
  • Traffic Generator. The system can be configured to generate arbitrary packet sequences, with custom timing, using a simple packet assembly API in C++. The primary use for this is in system debug and protocol error testing.
  • USB PD Demonstration Power Supply. Available firmware can configure the board to be a simple USB provider or consumer. An on board switching power supply provides 5V, 9V or 12V to the VBUS pins after PD provider negotiation.
  • Chip/IP Demonstrator. Key signals from the OTC9102 chip are available on headers. Hence the board provides a demonstration platform for the chip, and associated FPGA logic. Available host software can drive the chip in step by step mode to allow protocol operation to be followed.
  • Development Board. FPGA capability is provided by a daughter board with USB host interface API. This also works with the Xilinx development environment as platform for maintenance of the protocol logic and policy code. 

pdSysDiagramClr

Features

  • As delivered, supports USB Power Delivery Sniffer testing as well as development and testing of protocol code.
  • Compatible with 0.9 USB PD standard.
  • Communication with host via USB port. It can be self, or bus powered. A host driver API is included.
  • Software upgrade to include packet level host API.
  • On board discrete implementation of USB PD transceiver plus the option to switch to the OTC9101 IP demo chip when it becomes available.
  • On board Spartan-6 FPGA supports free Xilinx development tools.
  • Parallel USB-A and USB-B sockets, plus VBUS breakouts facilitate lab test connections.

Typical Applications

  • Early development of demonstration hardware for emerging USB Power Delivery standard.
  • USB PD sniffer hardware.
  • Development of generic data communication over DC power cords.

Deliverables

  • Motherboard/daughterboard system with USB cable.
  • Sniffer software.
  • Host demo API code.
  • Setup notes.
  • Pin mapping information.
  • Required code for FPGA factory configuration, including key buffering and CDR functions.

 

Service

  • One-year firmware and software updates.
  • 8 hours phone support. Available on, or off site consulting services at daily rates.

For source licensing terms, price, and delivery This email address is being protected from spambots. You need JavaScript enabled to view it., (949) 363-7982

OTC9101 USB Power Delivery Chip Layout

otc9101layout

USB Power Delivery BoardUSB Power Delivery Development/Test Board

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 The OTS9102 USB Power Delivery Demonstration and Development board version 4.4 is designed to assist in the development and testing of early market Power Delivery products.

The basic demo configuration of the board can be used learning system operation, compatibility testing, and production functional testing.

Source code is available for both the FPGA, and the CMOS Analog Front End chip as separate products.

Basic Features

  • 3A current available at 5V, 12V, and 15-20V.
  • Headers for investigation of critical PD signals.
  • Jumper configurable for provider or consumer roles at boot time.
  • Power terminals for consumer load.
  • 3.5" x 7" board has a connector for host interface.
  • Parallel USB standard PD A and micro AB connectors provided for PD.
  • A micro AB connector is provided for simulating PC or peripheral USB communications.
  • An Opal Kelly FPGA daughter board provides a well established FPGA development and USB host interface environment.
  • Supports 1.2 PD standard (including swap)
  • Uses Obsidian's OTC9102 analog front end chip.

pdSysDiagramClr

 

 

 

 

 

 Applications

  • USB PD Demonstrator. Key signals from the OTC9102 chip are available on headers. Hence the board provides a demonstration platform for the chip, and associated RTL. Available host software can drive the chip in step by step mode to allow protocol operation to be followed. 
  • USB PD Product Testing. Board can be configured as provider or consumer for bench testing other PD products. Since Obsidian has tested this board at the USB IF IOP meetings the board may be used to support compatibility testing.
  • Development Board. FPGA capability is provided by a daughter board with USB host interface API. This also works with the Xilinx development environment as platform for maintenance of the protocol logic and policy code.
  • Protocol Sniffer for debugging USB Power Delivery systems. With an available application, when daisy-chained between two USB PD systems, the Sniffer board produces an easy to read mnemonic listing of captured packets on a PC.
  • Traffic Generator. The system can be configured to generate arbitrary packet sequences, with custom timing, using a simple packet assembly API in C++. The primary use for this is in system debug and protocol error testing.

 

Price: $3300 per unit + shipping

Buy Now

 

highlights

2/21/17 - OT ships ams aH18 clock mutiplier PLL.

12/9/16 - New USB PD Development board.

5/22/16 - OT ships 130nm USB Type-C IP.

4/1/15 - Obsidian Announces USB 3.1 Cable Marker Chip. See more.

5/8/14 - Obsidian demonstates USB PD over Type-C. See more.

11/4/13 - Obsidian ships 4th PD IP version.

1/15/13 - Obsidian provides technology for CES demo.


 
USB Power Delivery IP

12/5/10 - 0.35µ Ip demo chip functional.