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Morphosys History

Funding

In 1997 Obsidian Technology and the University of California at Irvine (UCI) collaborated to develop a reconfigurable computing device concept that would be fundable under DARPA's reconfigurable computing project. This project had the ultimate goal of developing very high performance graphic data processing engines that could tackle such problems as automatic target identification in real time.

A proposal was submitted to DARPA containing some concepts produced by Obsidian Technology which was subsequently funded at $1.3M.

How the Architecture Developed

During the initial phase of the development the architecture was developed by Robert Heaton of Obsidian Technology and discussed weekly with co-researchers and intern students at UCI.

The initial plan had been to develop the concept of bit wide self configuring programmable logic, as laid out in the proposal. However, as Robert developed this against the target video processing algorithms provided by UCI it became clear that this methodology was a very inefficient in terms of silicon usage. 

This is because there is very little value in gate/flop level reconfigurability when the primitive steps for image processing are mostly arithmetic operations at a pixel level requiring at least pixel resolution data processing. Now, when the granularity of the architecture was increased to multiply accumulate (MAC) level the architecture began to strongly resemble a conventional SIMD array multiprocessor.

However, some elements of the reconfigurable computing paradigm could still be incorporated and it termed out that these had some positive effects on performance. (Also the ancillary benefit of still fitting the requirements to retain the DARPA funding!)

In particular, the wiring between the processor units could be changed at each instruction boundary. Hence, signals could flow through the processor array under program control. This is a much faster method than using some form of memory mapped inter-processor interface. It is almost as fast as hard wiring. This initial architecture was later written up in a paper by a UCI student.

Next, a more detailed architecture of the array processor unit was developed. This turns out to be a conventional ALU/MAC unit with resolutions tailored to the 8 bit per pixel World favored by the military customer. However, there are two exceptions: 

• The processor unit had hardware implemented register contexts built in. This formed part of the reconfigurability of the unit.

• Input muxing implemented not only various feedback options but also selection of inputs from other processor units. (The implementation of the configurable routing.)

Early Tools

Next it was necessary to develop some simple tools for programming the array in some meaningful way. Initially Obsidian developed an assembler embedded into Perl. However, providing instructions for 64 processors, even programming in rows, was rather unwieldy to debug.

Accordingly Obsidian developed a graphical tools based on tcl/tk called mview which showed the current instruction and current wiring for each processor in the array. A screen shot.

These tools were then transferred to the UCI project team.

Issues

The initial architecture was not optimal mostly due to the research nature of the project. The system had a fast transfer to an on-chip buffer RAM, but nevertheless each processor lacked local storage leading to something of bandwidth bottleneck. Also, the architecture is essentially a SIMD array with a narrow range of programmability    ram bandwidth, special purpose DSP engines, special software. These thoughts led to Obsidian's rRAM concept.

Continuing Development

Funding for the project development continued funded by DARPA and the US Air Force. Obsidian moved on to other developments but after a number of years the architecture continued to develop and is now a company, Morpho Technologies.