alu4

NASA/JPL "Simulogic" 4 Level Logic Test Chip.

Design

This project required a custom 4 level logic library to be designed and integrated into a test chip and sent to MOSIS within 40 days.

jpl_chip_layoutx300The test design comprise several 8 bit 4 level logic ALUs, plus an equivalent function implemented in binary standard cell logic for comparison.

This device used full custom layout for the four level logic (as shown right).

The equivalent binary ALU's were implemented using standard cells and standard cell place and route.

 

 

 

Device Verification

Obsidian has the in-house capability to design, layout, and populate small quantity boards for device verification and demonstration.

All the logic IO's on this device are 4 level. So a bench test/design verification required 4 level control of 40 IO's and the provision of 5 programmable variable bias levels/power supplies.

Software

Obsidian developed the software to control the design verification board through a USB interface. Use of a basic custom board allowed customized verification of the device at a fraction of the cost of other bench verification technologies.

jplLab